1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device in which word driver circuits are respectively divided and arranged within plural memory arrays.
2. Prior Art
Conventionally, in the semiconductor memory device of this kind, a word driver for operating a word line of a memory cell array is constructed by connecting an output to a metallic wiring such as aluminum backed to reduce a time constant of poly-silicon wiring connected to a gate of a memory cell and is arranged at the same pitch as the poly-silicon wiring and the aluminum wiring. However, the fine structure of a pattern is advanced as the capacity of an LSI is increased. Therefore, it has become difficult to pattern aluminum, etc. at the pitch of the poly-silicon wiring connected to the gate of the memory cell. Further, a memory cell portion is raised and it is difficult to pattern aluminum, etc. by a step caused on a boundary of the raised memory cell portion. Therefore, a divisional word driver system easy to escape passage of the aluminum wiring of the memory cell portion begins to be adopted in recent years as one of these solving measures.
FIG. 4 is a partial block diagram showing a constructional example of the conventional semiconductor memory device. With reference to FIG. 4, in this conventional semiconductor device, a main word driver 2, a main word driver for redundancy 3 and a memory array 1 are adjacent to each other and are arranged in a column direction. Plural pairs of these are arranged in row and column directions and a block is constructed with plural memory arrays arranged in the column direction as a unit. A divisional driver control circuit 4 is arranged in each column of each memory array 1. A sense amplifier 5 is arranged between respective columns of the memory arrays 1. A data amplifier 6 is arranged with respect to each block.
Each main word driver 2 and the main word driver for redundancy 3 are adjacent to each other and are arranged in the column direction for every memory array 1. As respectively illustrated in FIGS. 5 and 6, a main word driver control signal PX and internal X-address signals X2B.X3B.X4B, X2.X3B.X4B, X5B.X6B.X7B, X8.X9B.X10B, X8.X9B.X10 corresponding to first row address signal groups X2 to X10 of an input address signal are inputted and decoded. For example, respective main word signals MWL0 to MWLn and a main word line RMWL for redundancy for performing selective controls of respective word lines and a word line for redundancy are outputted to an upper side memory array of FIG. 4. Respective main word signals MWL0' to MWLn' and a main word signal RMWL' for redundancy for performing the selective controls of the respective word lines and the word line for redundancy are outputted to a lower side memory array of FIG. 4. Further, these main word drivers and the main word driver for redundancy are outputted with an internal raising voltage VBOOT as a high level.
Each memory array 1 has a cell array constructed by memory cells arranged in the row and column directions and including a memory cell for redundancy. Each memory array also has sub word drivers and a sub word driver for redundancy for selecting the respective word lines and the word line for redundancy in this cell array. The cell array, the sub word drivers and the sub word driver for redundancy are divisionally dispersed. For example, FIG. 7 is a block diagram showing a constructional example of the upper side memory array of FIG. 4. The respective sub word drivers and the sub word driver for redundancy input and decode control signals RA0 to RA3, RRA0 to RRA3, the respective main word signals MWL0 to MWLn and the main word signal RMWL for redundancy from the divisional driver control circuit. The respective sub word drivers and the sub word driver for redundancy respectively output word line signals WL0 to WL3 with respect to each of the main word signals MWL0 to MWLn, and output each of word line signals RWL0 to RWL3 for redundancy with respect to the main word signal RMWL for redundancy. At this time, one of each word line of the cell array and each word line for redundancy is selected and operated. Further, these sub word drivers and the sub word driver for redundancy are operated with the internal raising voltage VBOOT.
The divisional driver control circuit 4 is arranged in each column of each memory array and inputs and decodes second row address signal groups X0, X1, X10 of the input address signal and redundancy signals RED0, RED1, NRED. The divisional driver control circuit outputs control signals for controlling operations of each sub word driver and the sub word driver for redundancy within the memory array in each column. For example, FIG. 8 is a circuit diagram showing a constructional example of the divisional driver control circuit of FIG. 4. This divisional driver control circuit outputs control signals RRA0 to RRA3 on the basis of redundancy signals RED0, RED1 and outputs control signals RA0 to RA3 on the basis of the redundancy signal NRED. Each of the redundancy signals RED0, RED1 is a signal showing the selection of a redundancy address. The redundancy signal NRED is a signal showing that it is not a redundancy address. Therefore, the respective word line signals WL0 to WL3 and the word line signals RWL0 to RWL3 for redundancy within each memory array are not simultaneously selected and activated. Further, this divisional driver control circuit outputs the internal raising voltage VBOOT as a high level.
Each sense amplifier 5 is arranged between rows of the respective memory arrays and is connected between each bit line within an adjacent memory array 1 and a data input output line IO or IO'. Each sense amplifier 5 is selected, activated and controlled in accordance with a column address signal group of the input address signal. Each sense amplifier 5 amplifies, inputs and outputs each bit line data of the memory array 1.
A data amplifier 6 is arranged with respect to a pair of upper and lower each memory arrays 1 and is connected between the data input output line IO or IO' and a data bus line RWBS. Each data amplifier 6 is selected, activated and controlled in accordance with a data amplifier control signal DAE and internal X-address signals X8B.X9B, X8.X9B, X8B.X9, X8.X9 corresponding to first row address signals groups X8 to X9 of the input address signal. Each data amplifier amplifies, inputs and outputs data of the pair of upper and lower memory arrays.
This conventional semiconductor memory device is activated by a clock signal and an address signal provided from the exterior of this memory device and a specific memory cell is selected and the data are read/written. For example, the next explanation relates to an operation performed in a case in which internal X-address signals X0B, X1B, X2B.X3B.X4B, X5B.X6B.X7B, X8.X9B.X10B, X8.X9B, X10B corresponding to a row address signal of the input address signal are activated and its address signal does not show a redundancy address.
First, a main word driver control signal PX is set to a have a "high" voltage in accordance with the clock signal and the address signal so that a main word signal MWL0 and a main word signal RMWL for redundancy are activated. However, the redundancy signal NRED showing that it is not a redundancy address is active. The redundancy signals RED0, RED1 each showing a selection of the redundancy address are inactive. Accordingly, only a control signal RA0 is selected and activated and the other control signals RA1 to RA3, RRA0 to RRA3 are inactivate as they are. Accordingly, only a word line signal WL0 is selected and activated. The data of a memory cell inputting this word line signal WL0 thereto are outputted to a bit line. In a sense amplifier selected, activated and controller by an internal Y-address signal corresponding to a column address signal group of the input address signal, each bit line data are amplified, inputted and outputted between this sense amplifier and the data input output line IO or IO', Further, data are inputted and outputted to the exterior through each selected, activated and controlled data amplifier and a data bus line RWBS.
At this time, each data amplifier 6 is selected, activated and controlled in accordance with a data amplifier control signal DAE and internal X-address signals X8B.X9B, X8.X9B, X8B.X9, X8.X9 transmitted separately from internal X-address signals X8.X9B.X10B, etc. inputted to the main word drivers. Each data amplifier amplifies, inputs and outputs data to the exterior between this data amplifier and the data bus line RWBS.
The next explanation relates to an operation performed in a case in which internal X-address signals X0, X1B, X2B.X3B.X4B, X5B.X6B.X7B, X8.X9B.X10B, X8.X9B, X10B corresponding to a row address signal of the input address signal are activated and its address signal shows a redundancy address.
Also, in this case, a main word driver control signal PX is similarly set to have a "high" voltage in accordance with a clock signal and an address signal, and a main word signal MWL0 and a main word signal RMWL for redundancy are activated. However, the redundancy signal RED0 showing the selection of a redundancy address is active and the other redundancy signals RED1, NRED are inactive. Accordingly, only a control signal RRA1 is selected and activated and the other control signals RRA0, RRA2 to RRA3, RA0 to RA3 are inactive as they are. Therefore, only a word line signal RWL1 for redundancy is selected and activated. The data of a memory cell inputting this word line signal RWL1 for redundancy thereto are outputted to a bit line. Thereafter, similar to normal access, data are inputted and outputted to the exterior through the sense amplifier, the data amplifier, etc.
However, in the conventional semiconductor memory device, it is necessary to separately arrange wiring of the internal X-address signals corresponding to the row address signal of the input address signal with respect to a circuit such as the data amplifier unable to be arranged such that this circuit is adjacent to each main word driver and the main word driver for redundancy. Accordingly, a problem exists in that a layout area of the wiring of these internal X-address signals is large.
This is because it is difficult to pass the wiring through a memory array arranged between each main word driver, the main word driver for redundancy, and a circuit such as the data amplifier, etc.